The present invention relates to image processing circuits and more particularly to, a field-interpolation circuit for preventing the tremble of a screen in playing back a recorded image signal, by means of processing a frame of image signal by one-field photography and recording it when photographing a fast moving object in a digital still video camera.
The digital still video camera system comprises a camera as shown in FIG. 1 and a player as shown in FIG. 2.
The digital still video camera shown in FIG. 1 is an apparatus for converting a photographed image signal to a digital data and recording it into a memory card 1 for use as a recording medium, and the digital still video player shown in FIG. 2 is an apparatus for reading out an image signal recorded in the memory card 1 and displaying it on a television monitor.
When an object is photographed, a focusing can be achieved by manipulation of a lens, similar to conventional cameras, and a shutter speed can also be selected among many choices, although these functional blocks are not shown in FIG. 1.
As the shutter, an electronic shutter of which the speed is controlled by the charge storage time of a charge coupled device (CCD) 101 is widely used.
FIG. 1 shows the camera circuit diagram of a conventional digital still video camera system comprising a memory card 1, a white balance (WB) sensor 2, a first interface circuit 3, a selector 4, a display 5, a central processing unit (CPU) 111, a second interface circuit 112, a signal generator 113, a photographing means 100, a gamma and WB compensating circuit 104, a low pass filter (LPI) 105, an analog-to-digital (A/D) converter 106, a signal converting device 600, and a recording device 700.
In FIG. 1, the photographing device 100 comprises a CCD 101, a sampler-and-holder 102, an amplifier 103, and a CCD driver 114.
The signal converting device 600 comprises a signal processor 107, a low-sensitivity pre-filter 108, a sub-sampler 109, a data compressor 110, and a switching circuit 115.
Also, the recording device comprises a memory interface circuit 116, a buffer memory 117, and a data generator 118.
FIG. 2 shows the player circuit diagram of a conventional digital still video camera system.
Now the operation of a total system is briefly described with reference to FIG. 1 and FIG. 2.
First, if an user turns on the power of the camera circuit shown in FIG. 1, a message representing a present state of the camera appears on the display 5.
Subsequently, if the user presses a release button (not shown in figures) by a half after selecting a desirable photographic mode using the selector 4, the CPU 111 recognizes this selection and provides electronic powers to each electronic circuit.
Then if an exposure sensor measures the intensity of an incident light 6 and transmits the measured result to the CPU 111, the CPU 111 controls an iris according to the measured intensity data (this is well known and thus is not shown in FIG. 1 and FIG. 7).
Also, an external color temperature is measured by the WB sensor 2; and this measured data is provided as information for white balance to the CPU 111 through the first interface circuit 3.
In this state, if the release button is completely pressed, the CPU 111 operates the shutter and performs the photographing and signal-processing operation by controlling the signal generator 113 according to the information for the white balance and the exposed light intensity.
Then the signal generator 113 provides control signals to the CCD driver 114, the sampler-and-holder 102, the amplifier 103, the gamma and WB compensator 104, the A/D converter 106, the data compressor 110, and the switching circuit 115, according to the shutter speed under control of the CPU 111.
Then, the CCD 101 photographs the object and provides the image signal by an optical-to-electrical conversion, driven by the CCD driver, and this image signal is applied to the gamma and WB compensator 104 through the sampler-and-holder 102 and the amplifier 103.
The gamma and WB compensator 104 performs the gamma and WB compensation of the image signal by the control of the CPU 111 through the second interface circuit 112.
This compensated image signal is filtered by the LPF 105 and is subsequently converted to a digital image signal by the A/D converter 106.
The digital image signal is divided into a luminance signal Y1 and color-difference signals CR1 and CB1 by the signal processor 107.
On the other hand, since the image signal from the CCD 101 is not time-continuous, it is converted to a time-continuous signal by the sampler-and-holder 102 and is subsequently applied to the amplifier 103.
In another words, a signal, as shown in FIG. 3(B), provided from the CCD 101 which is driven by a CCD driving clock, as shown in FIG. 3(A) provided from the CCD driver 114, (i.e., a difference between a reference potential and a stored charge potential of each pixel of the CCD 101) is held during one period of the CCD driving clock by the sampler-and-holder 102 as shown in FIG. 3(C).
The amplifier 103 amplifies the output signal of the sampler-and-holder 102 up to an input signal level of the A/D converter 106.
Then the A/D converter 106 samples the output signal of the sampler-and-holder (FIG. 3(C)) 102 which is applied through the LPF 105, during the high or low level of a control signal of the signal generator 113, i.e., a sampling clock shown in FIG. 3D, and converts it to the digital image signal.
The digital signal is divided into the luminance signal Y1 and the color-difference signals CR1 and CB1 by the signal processor 107 and they are filtered by the low-sensitivity pre-filter 108 according to the selected mode.
Subsequently, the data of the filtered signals are compressed by the sub-sampler 109 and the data compressor 110.
The low-sensitivity pre-filter 108 is a digital filter for preventing the aliasing resulting from the sub-sampling of the sub-sampler 107. The low-frequency prefilter 108 is used to remove frequency components above half a sub-sampling frequency of the luminance signal Y1 and the color difference signals CR1 and CB1.
As for the low-sensitivity pre-filter, a FIR filter is use since it has no group delay.
The sub-sampler 109 compresses the data of the luminance signal Y1 and the color-difference signal CR1 or CB1 filtered by the low-sensitivity pre-filter 108 by a half line offset sub-sampling.
Subsequently, the data compressor 110 further compresses the sub-sampled data by a conventional data compression method, reducing the number of necessary bits per pixel.
The conventional data compression method, used can be a transform coding method delta pulse code modulation method (DPCM), an adaptive delta pulse code modulation method (ADPCH) and so on.
The sample points of the output of the signal processor 107 are shown in FIG. 4, while the sample points of the output of the sub-sampler 109 are shown in FIG. 5.
On the other hand, before the photograph of the object, the user can select a data format to be recorded into the memory card 1 by manipulation of the selector 4.
Among many modes having different screen qualities, desired mode is selected and, according to the selected mode, the amount of digital data for one frame of a still image is changed, i.e., the number of frames of the still image to be recorded into the memory card 1 can be changed.
The selector 4 can select between one of a first to a fourth mode and, according to the mode selection of the selector 4, the CPU 111 controls the signal generator 113, the switching circuit 115, and the memory interface circuit 116, for recording the image signal with the different data amount to the memory card 1 through the buffer memory 117 as wells as the control signal such as a data compression mode signal and an address signal.
For example, when the memory capacity of one memory card is 18 Mbit and the amount of data for one frame of image signal is 6 Mbit, the data recording into the memory card 1 according to each mode is as follows.
First, if the first mode is selected, the output of the signal processor 107 is provided from the switching circuit 115 and is recorded into the memory card without the data compression.
Thus, in the first mode case, three frames of the image signal, i.e., three sheets of the still images can be recorded.
Second, if the second mode is selected, the output of the sub-sampler 109 is provided from the switching circuit 115 and is recorded into the memory card 1.
In this case, the amount of the recorded data is 3 Mbit corresponding to half of the amount of the output data of the signal processor 107 for each game since the output of the sub-sampler 109 is the sub-sampled data as shown in FIG. 5.
Thus, in the second mode case, six frames, i.e., six sheets of still images can be recorded.
Third, if the third mode or fourth mode is selected, the output of the data compressor 110 is provided from the switching circuit 115 and is recorded into the memory card 1.
The data compressor compresses the input data by a factor of 1/2 in the third mode, while compressing it by a factor of 1/4 in the fourth mode.
Thus, if the third mode is selected, the amount of the data recorded into the memory card 1 is 1.5M bit corresponding to one fourth of the amount of the output data of the signal processor 107.
Thus, in the third mode case, twelve frames, i.e., twelve sheets of still images can be recorded.
On the other hand, in the fourth mode case, the amount of the data recorded into the memory card 1 is 750K bit corresponding to 1/8 of the output data of the signal processor 107.
Thus, twenty four frames, i.e., twenty four sheets of still images can be recorded.
If, as the data compression method, a discrete cosine transform (DCT) that minimizes the redundancy of the image data is used, the data compression can be performed without degradation of image quality even to about 1/20 of the amount of the output of the signal processor 107 so that some modes to more compress the data can be established.
On the other hand, as the information being recorded into the memory card 1, there is also provided a screen number from the data generator 118 by the control of the CPU 111 and other wanted data to be recorded onto a particular image, as well as the image data.
Now the operation of the digital still video player, shown in FIG. 2, for playing back the image data recorded in the memory card 1 by the digital still video camera circuit shown in FIG. 1, is described in detail.
If the user inserts the memory card 1 into the digital still video player shown in FIG. 2 and assigns a file number (an image number) by manipulation of a key board 213, the CPU 201 reads the information of directory regions of the memory card 1 through a card interface circuit 202.
Then the CPU 201 classifies information for the assigned file number to check the recognition of the image data, the image processing method and the data compression mode. Accordingly, in response to this information, the CPU 201 controls a signal processing path.
To describe this in detail, a mode signal is provided from the card interface circuit 202 according to the information in the memory card 1 and is applied to a decision circuit 211 via the CPU 201.
Then the decision circuit 211 decides the data compression mode and, according to the decided mode, controls a switch 205 to connect the output signal of either a data reconstruction circuit 203 or a card interface circuit to an interpolation circuit 206.
For example, if the selected file is an image which was recorded in the third or fourth mode by the digital still video camera circuit shown in FIG. 1, the data provided from the card interface circuit 202 is extended by a factor of 2 or 4 and is subsequently reconstructed by the data reconstruction circuit 203.
The reconstructed data is applied to the interpolation circuit 206 through the switch 205.
Then the data is interpolated by the interpolation circuit 206 and is divided into a luminance signal Y and two color-difference signals CR and CB.
These signals are provided to a frame memory 207 so that one frame of data is recorded.
On the other hand, if the selected file is an image which was recorded in the first or second mode, the data provided from the card interface circuit 202 is applied directly to the interpolation circuit 206 through the switch 205, without passing the data reconstruction circuit 203.
Similarly, the data is interpolated by the interpolation circuit 206 and the luminance signal Y and the color-difference signals CR and CB are provided to the memory 207, recording one frame of data.
Also, other data such as the control data provided from the card interface circuit 202 as well as the image data is recorded into the frame memory 207 through a data circuit 204.
After one frame of data is recorded into the frame memory 207, the luminance signal Y and the color-difference signals CR and CB are converted to an analog signal by a D/A converter 209, in synchronous with a clock provided from the signal generator 215 which is controlled by the CPU 201.
The output signals of the D/A converter 209 become smooth by low pass filters (not shown in FIG. 2) and are respectively applied to an encoder and matrix circuit 210.
Then the outputs of the D/A converter 209 are converted to a composite image signal or R(Red), G(Green), and B(Blue) components by the encoder and matrix circuit 210 and these signals are displayed on a monitor.
As described hereinabove, when the video still camera shown in FIG. 1 photographs the object with the CCD 101 for use as the image device, a first field is photographed for 1/60 seconds and subsequently a second field is photographed for the next 1/60 seconds.
At that time, if a fast moving object is photographed, the first field is photographed at a position S as shown in FIG. 6(A), while the second field is photographed at another position s' as shown in FIG. 6(B).
Thus, if the photographed image is played back by the digital still video player shown in FIG. 2 and is displayed on the monitor 216, different screens are displayed every 1/60 seconds.
Thus, there is a problem that the screen is trembled with a period of 1/60 seconds. The present invention overcomes this problem and provide a field interpolation circuit and method thereof that prevent the tremble of a screen in playing back a recorded image signal, by means of generating one frame of image signal by one field photography in recording a fast moving object and recording it after signal processing.
According to the first aspect of the present invention, there is provided a field interpolation circuit, including a digital still video recorder for recording or playing back an image signal, the circuit comprising:
a memory card with a predetermined memory size for recording and playing back data, a selector for selecting a photography mode and a data compression mode, a CPU for controlling an overall system according to the mode selected by the selector, a signal generator, connected to the CPU through an interface circuit, for providing control signals according to the control of the CPU, a photographing means, including a photographing device, for photographing an object by using the photographing device according to the control signals from the signal generator and converting an photographed optical signal to an electrical signal and providing a continuous image signal by sampling-and-holding a time-incontinuous image signal, an A/D converter for converting the output signal of the photographing means to digital image signal according to the control signals of the signal generator;
a first field memory for storing and providing a first field of the digital image signal according to control signals;
a field converter for converting the first field image signal to a second field image signal by arithmetic operation according to the structure of the photographing device under control of the signal generator and the CPU;
a second field memory for selectively storing and providing the second field image signals provided from the A/D converter and the field converter according to control signals;
a frame memory controller for controlling the first and second field memories under control of the signal generator and the CPU;
a signal conversion device for dividing the image signal provided from the first and second field memories into a luminance signal and two color-difference signals according to the control signals of the signal generator and providing an image signal which has the different amount of data according to the mode selected by the selector, after low-sensitivity filtering, sub-sampling, and data compressing; and
a recording device for recording the output image signal of the signal converting device as well as other image information into the memory card.
According to a second aspect of the present invention, there is provided a method for field-interpolation, including a CPU, a signals generator, a photographing means, an A/D converter, a second field memory, and frame memory controller, the method comprising:
a photographing process for photographing an object by using a photographing device such as CCD, and providing a first field image signal after converting the frame-stored charge of the photographing device to an electrical image signal;
a digital converting process for converting the first-field image signal in the photographing process to a digital image signal using the A/D converter;
a storing process for storing the digital first-field image signal in the digital converting process into the first field memory; a field interpolating process for emphasizing a larger correlative side of image signals on upper and lower horizontal lines adjacent to the first field image signal by logic arithmetic operation, and, for storing a second field image signal into the second field memory after converting the first field image signal to the second field image signal; and
an output process for providing the first and second field image signals stored in the storing process and the field interpolating process.